Magnetic tunneling junctions (MTJs) and GMR/Spin Valve (SV), with two ferromagnetic layers separated by a non-magnetic layer (a tunneling dielectric layer for MTJs and a transitional metal for GMR/SV), have been widely studied for use as a memory element (such as in MRAM). Usually one of the ferromagnetic layers has a fixed magnetization direction (the pinned layer) while the other layer is free to switch its magnetization direction (the free layer).
For MRAM applications, the magnetic stack (MTJ or GMR/SV) is usually shaped so as to exhibit shape anisotropy. Shape anisotropy is present whenever the shape of the storage element deviates from a circle, e.g. an ellipse. In its quiescent state, the free layer magnetization lies along the long axis of the cell either parallel or anti-parallel to the direction of magnetization of the pinned layer (see arrows in FIG. 1a). This long axis is referred to as the easy axis (x), the direction perpendicular to it being the hard axis (y). A cross sectional view of this for the case of a MTJ element is shown in FIG. 1b, with element 11 representing the free layer, element 12 the dielectric tunneling layer, and element 13 the pinned layer.
Digital information is thus stored according to the direction of magnetization of the free layer. FIG. 2 shows the resistance R of such a MTJ element as a function of external field Hs along the orientation of the pinned layer magnetization. When the field is off, the two states with minimum and maximum resistances correspond to the free layer magnetization being parallel and anti-parallel to the pinned layer magnetization respectively. The field required to switch between the two states (Hs) is determined by the shape anisotropy energy of the element. When an additional external field is simultaneously applied in the hard axis direction at the same time, the value of Hs is reduced, becoming zero when the hard axis field reaches a particular value (Hy_sat).
In MRAM applications, both the external fields used to program the MRAM cell are provided by current lines. As shown in FIG. 3a, bit line 31 provides the easy axis field while word line 32 provides the hard axis field. To program a cell, both bit and word line currents are applied. The combination of these two fields overcomes the shape anisotropy to set the magnetization of the selected cell into the desired direction. This cell is referred to as a selected cell. Due to process/film property variations, there will be some variation in the shape anisotropy so the combined value of bit/word line fields needed to write each selected cell also varies. To reliably write all selected memory cells, the bitline and wordline current (shown in the figure as Ibit and Iword, respectively) have to have been chosen to be able to write the cell will highest shape anisotropy.
However, while writing the selected cell, many other cells that lie under the bit line or the word line (but not both) that are not intended to be programmed experience the field of either the bit or word line current. Although this field is smaller than the combined field experienced by the selected cell, these cells can still be accidentally programmed, thereby causing an error. These cells are referred to as half-select cells. The probability of a half-selected cell being accidentally written depends on the value of the applied bitline or wordline current, Hs and Hy_Sat, the higher the bit/word line current and the smaller the Hs or Hy_sat, the easier it is for a half-select error to occur. Again, there are variations in Hs and Hy_sat. So the values of both the bit and word currents must be carefully chosen—too low and the selected cell cannot be reliably programmed, too high and they will cause errors on half-selected cells.
The window for programming an MRAM is determined by 3 boundaries: the combined field from both bit and word lines needed to reliably write the selected cells, the distance between the bit line field and the smallest Hs at which Iword=0, and the distance between the word line field and the smallest Hy_sat. It is crucial to have a window large enough for the reliable programming of selected cells yet small enough to not cause half-select errors. The window can be enlarged by increasing the shape anisotropy value but this approach demands higher bit and word currents which is not desirable for high density applications.
An alternative approach (U.S. Pat. Nos. 6,798,690B1 and 6,798,691 B1) is to increase Hs at Iword=0 while maintaining Hs at Iword, by confining the free layer magnetization configuration to the “C-state”. The method to achieve this is by patterning the MTJ cell into certain curved shapes. The “C-state” will have much higher Hs, as described by Ref.[1]. As shown in FIG. 4, Hs for a small hard axis field, is significantly greater in the C-switching mode 44 than in the conventional rotational switching mode. In the high hard axis field region, the switching behavior of the C-state returns to the normal rotational mode. Thus, for C-state cells, the distance between the bit line field and the smallest Hs at Iword=0 is significantly increased. Note that FIG. 3b also shows a pair of lines (current source/sink) shared by both segments. Also shown in FIG. 3b is the enable gate that activates these lines as needed.
This approach will significantly reduce the probability of half-select errors under the bit line. The programming window now is mainly defined by the writing field needed to write the selected cell and the distance between the word line field and the smallest Hy_sat. The MRAM write operating points, 41 and 42, for these two prior art approaches are set near the inflection point 43 of the curves, as indicated in FIG. 4. The problem with this operating point is that the inflection point at which the switching mode changes from C-state to normal rotational switching, has a very wide distribution, as indicated by the dashed curves in FIG. 4. This causes significantly increased variation in the field needed to write the selected cells, which greatly reduces the operating window.
Another approach to handling half-select issues along bit and word line is the segmented write architecture (U.S. Pat. Nos. 6,335,890 and 6,490,217). This is illustrated in FIG. 3b. It provides a technique for overcoming the limitations of conventional write selection schemes. By way of example only, a write operation directed to a specific segmented group, e.g., 334 in FIG. 3b will now be described:
Select line memory array 300 directs the application of a destabilizing hard axis magnetic field to a subset of memory cells, namely, those memory cells associated with segmented group 334. All memory elements 342, 344 within the selected segmented group 334 are written simultaneously. An unselected segmented group (e.g., 336), sharing a common write word line 386 with segmented group 334, does not receive a half-select field along its hard axis even when the group select switch (e.g., 376) corresponding to the unselected segmented group 336 is enabled. This is primarily due to the fact that only one segmented bit slice among adjacent segmented bit slices, e.g., segmented bit slices N and N+1, can receive a destabilizing write current at any given time.
Consequently, the magnitude of the hard axis field can be increased with no danger of disturbing the state of an unselected memory cell. Since all memory cells experiencing a hard axis field will, by definition, be written simultaneously, there are no half-selected memory cells along the word dimension using the segment write architecture.
The operating point 45 for a selected memory cell in the segmented write architecture is also shown in FIG. 4. Seen there is a plot of the required switching field as a function of the hard axis field (both normalized by being shown as fractions of the saturation field Hy_sat). On this part of the operating curve, the magnitude of the easy axis field (used to write the selected cell) can be substantially decreased. The write margin between selected and half-selected cells is significantly increased. Moreover, because a large easy axis field is not required by the select line architecture of the invention, the bit line current required to write the memory cells can be significantly reduced, thereby reducing the overall write current required by the memory array 300.
An example of a C-shape is shown by FIG. 5a. The free layer magnetizations at the two tip regions have been arranged to be at an angle to its central region, tilted toward its hard axis direction with the magnetization components perpendicular to the hard axis located opposite to each other. The tip regions serve as the nucleation sites for inducing the C switching. The angle of a tip region with respect to the central region can be varied from 10 to greater than 90 degree.
In addition to the references cited above, the following references of interest were also found:
U.S. Pat. No. 6,272,040 (Salter et al) shows a method to program more than one coupled memory cell using a medium current level. U.S. Pat. No. 6,594,191 (Lammers et al) teaches that only memory cells in a selected segment get a hard axis high field. U.S. Pat. No. 7,020,015 (Hong et al) shows shape anisotropy with edge or tip portions in the “pacman” shape.